Fundamental Network Processor Performance Bounds

In this paper, fundamental conditions which bound the network processing unit (NPU) worst-case performance are established. In particular, these conditions formalize and integrate, with mathematical rigor, two existing approaches for finding the NPU performance bounds, i.e., the work conserving condition and instruction/latency budget based approaches. These fundamental conditions are then employed to derive tight memory access latency bounds for a data path flow with one memory access. Finally, one of these memory access latency bounds is successfully used to interpret a peculiar phenomenon found in Intel IXP1200, demonstrating the importance of analytical modeling for NPU performance analysis.

• Type: Conference
• Year: 2005
• Where: NCA
• Authors: Hao Che, Chethan Kumar, Basavaraj Menasinahal
• Keywords: Access Latency Bounds, Fundamental Conditions, Memory Access Latency, NCA 2005, Network Computing