A Fused Hybrid Floating-Point and Fixed-Point Dot-Product for FPGAs

Dot-products are one of the essential and recurrent building blocks in scientific computing, and often take-up a large proportion of the scientific acceleration circuitry. The acceleration of dot-products is very well suited for Field Programmable Gate Arrays (FPGAs) since these devices can be configured to employ wide parallelism, deep pipelining and exploit highly efficient datapaths. In this paper we present a dotproduct implementation which operates using a hybrid floating-point and fixed-point number system. This design receives floating-point inputs, and generates a floating-point output. Internally it makes use of a configurable word-length fixed-point number system. The internal representation can be tuned to match the desired accuracy. Results using a high-end Xilinx FPGA and an order 150 dot-product demonstrate that, for equivalent accuracy metrics, it is possible to utilize 3.8 times fewer

• Type: Conference
• Year: 2010
• Where: ARC
• Authors: Antonio Roldao Lopes, George A. Constantinides
• Keywords: ARC 2010, Hardware, Recurrent Building Blocks, Scientific Acceleration Circuitry, fixed-point Number System