GasP Control for Domino Circuits

We present two novel asynchronous control circuits for domino pipelines. The control circuits are based on GasP circuits, have a minimum cycle time of six gate delays, and compare favorably with previously published control circuits. We present some results from a chip implementation of several 64-bit domino adders in a TSMC CMOS 180 nm process technology.

• Type: Conference
• Year: 2005
• Where: ASYNC
• Authors: Jo C. Ebergen, Jonathan Gainsley, Jon K. Lexau, Ivan E. Sutherland
• Keywords: ASYNC 2005, Asynchronous Control Circuits, Control Circuits, GasP Circuits, Hardware