Generation of Test Patterns for Differential Diagnosis of Digital Circuits

In a faulty digital circuit, many (single) faulty gates may explain the observed findings. In this paper we are mostly concerned, not in obtaining alternative diagnoses, but rather to differentiate the available candidates. Although techniques exist that generate test patterns for verifying whether one specific gate is faulty, these techniques do not identify test patterns that discriminate between alternative faulty gates. This paper extends one such technique, developed for a constraint logic programming framework, in order to generate differential test patterns. This technique allows the elimination of diagnostic candidates requiring no expensive generate and test procedure. To support our approach we present some experimental results obtained using the standard ISCAS benchmark circuits. We analyse the performance of our basic algorithm and the improvements obtained with some optimisation techniques.

• Type: Conference
• Year: 1998
• Where: CP
• Authors: Francisco Azevedo, Pedro Barahona
• Keywords: Artificial Intelligence, CP 1998, Faulty Digital Circuit, Faulty Gates, Test Patterns