A Generic Multi-Phase On-Chip Traffic Generation Environment

We present hereafter a framework for on-chip traffic generation and networks-on-chip performance evaluation. This framework is based on a traffic generator that has three important characteristics: the splitting of traffic generation in multiple phases, the ability to replay a previously recorded trace in various interconnect systems, and the capacity to produce stochastic traffic with advanced statistical properties. We focus here on the second characteristics, by validating it in cycle-accurate SystemC simulations.

• Type: Conference
• Year: 2006
• Where: ASAP
• Authors: Antoine Scherrer, Antoine Fraboulet, Tanguy Risset
• Keywords: ASAP 2006, Hardware, Networks-on-chip Performance Evaluation, On-chip Traffic Generation, Traffic Generation