A generic multilevel multiplying D/A converter for pipelined ADCs

—State-of-art implementations of pipelined ADCs can only realize a multiplying DAC (MDAC) with (2n –1) levels. However, the number of levels needed to optimize the performance may differ from this number. A novel scheme is proposed allowing for realization of an arbitrary number of MDAC levels, while allowing for 1 bit of digital redundancy and digital error correction without any overhead.

• Type: Conference
• Year: 2005
• Where: ISCAS
• Authors: Vivek Sharma, Un-Ku Moon, Gabor C. Temes
• Keywords: Digital Error Correction, ISCAS 2005, Multiplying Dac, —State-of-art Implementations