GPU-Accelerated High-Level Synthesis for Bitwidth Optimization of FPGA Datapaths

Bitwidth optimization of FPGA datapaths can save hardware resources by choosing the fewest number of bits required for each datapath variable to achieve a desired quality of result. However, it is an NP-hard problem that requires unacceptably long runtimes when using sequential CPU-based heuristics. We show how to parallelize the key steps of bitwidth optimization on the GPU by performing a fast brute-force search over a carefully constrained search space. We develop a high-level synthesis methodology suitable for rapid prototyping of bitwidth-annotated RTL code generation using gcc’s GIMPLE backend. For range analysis, we perform parallel evaluation of sub-intervals to provide tighter bounds compared to ordinary interval arithmetic. For bitwidth allocation, we enumerate the different bitwidth combinations in parallel by assigning each combination to a GPU thread. We demonstrate up to 10–1000× speedups for range analysis and 50–200× speedups for bitwidth allocation when compa...

• Type: Journal
• Year: 2016
• Where: FPGA
• Authors: Nachiket Kapre, Deheng Ye
• Keywords: FPGA, FPGA 2016