Graph-based evolutionary design of arithmetic circuits

Abstract--In this paper, we present an efficient graph-based evolutionary optimization technique called evolutionary graph generation (EGG) and the proposed approach is applied to the design of combinational and sequential arithmetic circuits based on parallel counter-tree architecture. The fundamental idea of EGG is to employ general circuit graphs as individuals and manipulate the circuit graphs directly using new evolutionary graph operations without encoding the graphs into other indirect representations, such as bit strings used in genetic algorithm (GA) proposed by Holland and trees used in genetic programming (GP) proposed by Koza et al. In this paper, the EGG system is applied to the design of constant-coefficient multipliers and the design of bit-serial data-parallel adders. The results demonstrate the potential capability of EGG to solve the practical design problems for arithmetic circuits with limited knowledge of computer arithmetic algorithms. For example, in the design o...

• Type: Journal
• Year: 2002
• Where: TEC
• Authors: Dingjun Chen, Takafumi Aoki, Naofumi Homma, Toshiki Terasaki, Tatsuo Higuchi
• Keywords: Arithmetic Circuits, Designs, Evolutionary Graph, TEC 2002