Hardware Implementation Trade-Offs of Polynomial Approximations and Interpolations

This paper examines the hardware implementation trade-offs when evaluating functions via piecewise polynomial approximations and interpolations for precisions of up to 24 bits. In polynomial approximations, polynomials are evaluated using stored coefficients. Polynomial interpolations, however, require the coefficients to be computed on-the-fly by using stored function values. Although it is known that interpolations require less memory than approximations, but at the expense of additional computations, the trade-offs in memory, area, delay, and power consumption between the two approaches have not been examined in detail. This work quantitatively analyzes these trade-offs for optimized approximations and interpolations across different functions and target precisions. Hardware architectures for degree-1 and degree-2 approximations and interpolations are described. The results show that the extent of memory savings realized by using interpolation is significantly lower than what is com...

• Type: Journal
• Year: 2008
• Where: TC
• Authors: Dong-U Lee, Ray C. C. Cheung, Wayne Luk, John D. Villasenor
• Keywords: Approximation, Information Technology, Piecewise Polynomial Approximations, Polynomial Approximations, TC 2008