Hardware Natural Language Interface

In this paper an efficient architecture for natural language processing is presented, implemented in hardware using FPGAs (Field Programmable Gate Arrays). The system can receive sentences belonging to a subset of Natural Languages (NL) from the internet or as SMS (short message service). The recognition task of the input string uses Earley’s parallel parsing algorithm and produces intermediate code according to the semantics of the grammar. The intermediate code can be transmitted to a computer, for further processing. The high computational cost of the parsing task in conjunction with a possible large amount of input sentences, to be processed simultaneously, justify the hardware implementation of the grammar (syntax and semantics). An extensive illustrative example is given from the area of question answering, in order to show the feasibility of the proposed system.

• Type: Conference
• Year: 2007
• Where: IFIP12
• Authors: Christos Pavlatos, Alexandros C. Dimopoulos, George K. Papakonstantinou
• Keywords: Earley’s Parallel Parsing, IFIP12 2007, Information Technology, Intermediate Code, Natural Languages