Hardware-software co-design of embedded reconfigurable architectures

In this paper we describe a new hardware/software partitioning approach for embedded reconfigurable architectures consisting of a general-purpose processor (CPU), a dynamically reconfigurable datapath (e.g. an FPGA), and a memory hierarchy. We have developed a framework called Nimble that automatically compiles system-level applications specified in C to executables on the target platform. A key component of this framework is a hardware/software partitioning algorithm that performs finegrained partitioning (at loop and basic-block levels) of an application to execute on the combined CPU and datapath. The partitioning algorithm optimizes the global application execution time, including the software and hardware execution times, communication time and datapath reconfiguration time. Experimental results on real applications show that our algorithm is effective in rapidly finding close to optimal solutions.

• Type: Conference
• Year: 2000
• Where: DAC
• Authors: Yanbing Li, Tim Callahan, Ervan Darnell, Randolph E. Harr, Uday Kurkure, Jon Stockwood
• Keywords: DAC 2000, Datapath Reconfiguration Time, Design Automation, Hardware/software Partitioning Algorithm, Hardware/software Partitioning Approach