Heads and tails: a variable-length instruction format supporting parallel fetch and decode

Abstract. Existing variable-length instruction formats provide higher code densities than fixed-length formats, but are ill-suited to pipelined or parallel instruction fetch and decode. This paper presents a new variable-length instruction format that supports parallel fetch and decode of multiple instructions per cycle, allowing both high code density and rapid execution for high-performance embedded processors. In contrast to earlier schemes that store compressed variable-length instructions in main memory then expand them into fixed-length in-cache formats, the new format is suitable for direct execution from the instruction cache, thereby increasing effective cache capacity and reducing cache power. The new head-andtails (HAT) format splits each instruction into a fixed-length head and a variable-length tail, and packs heads and tails in separate sections within a larger fixed-length instruction bundle. The heads can be easily fetched and decoded in parallel as they are a fixed dis...

• Type: Conference
• Year: 2001
• Where: CASES
• Authors: Heidi Pan, Krste Asanovic
• Keywords: CASES 2001, System Software, Variable-length Instruction Format, Variable-length Instructions, Variable-length Tails