Heterogeneous Architecture Exploration: Analysis vs. Parameter Sweep

This paper argues the case for the use of analytical models in FPGA architecture layout exploration. We show that the problem when simplified, is amenable to formal optimization techniques such as integer linear programming. However, the simplification process may lead to inaccurate models. To test the overall methodology, we combine the resulting layouts with VPR 5.0. Our results show that the resulting architectures are better than those found using traditional parameter sweeping techniques. Key words: Floorplanning; Reconfigurable architectures; FPGA; integer linear programming (ILP)

• Type: Conference
• Year: 2009
• Where: ARC
• Authors: Asma Kahoul, George A. Constantinides, Alastair M. Smith, Peter Y. K. Cheung
• Keywords: ARC 2009, Formal Optimization Techniques, FPGA Architecture Layout, Hardware, Integer Linear Programming