High-level synthesis under I/O Timing and Memory constraints

The design of complex Systems-on-Chips implies to take into account communication and memory access constraints for the integration of dedicated hardware accelerator. In this paper, we present a methodology and a tool that allow the High-Level Synthesis of DSP algorithm, under both I/O timing and memory constraints. Based on formal models and a generic architecture, this tool helps the designer to find a reasonable trade-off between both the required I/O timing behavior and the internal memory access parallelism of the circuit. The interest of our approach is demonstrated on the case study of a FFT algorithm.

• Type: Journal
• Year: 2006
• Where: CORR
• Authors: Philippe Coussy, Gwenolé Corre, Pierre Bomel, Eric Senn, Eric Martin
• Keywords: CORR 2006, Education, Memory Access, Memory Access Constraints, Memory Access Parallelism