A High-Performance Asynchronous FPGA: Test Results

We report test results from a prototype asynchronous FPGA (AFPGA) implemented in TSMC’s 0.18μm CMOS process. The AFPGA uses SRAM-based configuration bits with pipelined logic blocks and switch boxes. Test results

• Type: Conference
• Year: 2005
• Where: FCCM
• Authors: David Fang, John Teifel, Rajit Manohar
• Keywords: FCCM 2005, Hardware, Pipelined Logic Blocks, Prototype Asynchronous Fpga, Tsmc’s 0.18μm Cmos