High performance encryption cores for 3G networks

This paper presents two novel and high performance hardware architectures, implemented in FPGA technology, for the KASUMI block cipher; this algorithm lies at the core of the confidentiality and integrity algorithms defined for the Universal Mobile Telecommunication System (UMTS) standard. The first proposal is a pipelined design and the second implements an iterative approach. The throughput for these architectures turn out to be higher than the throughput achieved by other proposals. Categories and Subject Descriptors E.3 [Data Encryption]: standards; C.3 [Special-Purpose and Application-Based Systems]: real-time and embedded systems General Terms Algorithms, Performance, Design, Security Keywords 3G, UMTS Security Architecture, KASUMI, FPGA

• Type: Conference
• Year: 2005
• Where: DAC
• Authors: René Cumplido, Tomás Balderas-Contreras
• Keywords: DAC 2005, Design Automation, KASUMI Block Cipher, Performance Hardware Architectures, UMTS Security Architecture