A high-performance FPGA architecture for restricted boltzmann machines

Despite the popularity and success of neural networks in research, the number of resulting commercial or industrial applications have been limited. A primary cause of this lack of adoption is due to the fact that neural networks are usually implemented as software running on general-purpose processors. Algorithms to implement a neural network in software are typically O(n2 ) problems – as a result, neural networks are unable to provide the performance and scalability required in non-academic settings. In this paper, we investigate how FPGAs can be used to take advantage of the inherent parallelism in neural networks to provide a better implementation in terms of scalability and performance. We will focus on the Restricted Boltzmann machine, a popular type of neural network, because its architecture is particularly well-suited to hardware designs. The proposed, multi-purpose hardware framework is designed to reduce the O(n2 ) problem into an O(n) implementation while only requiring O...

• Type: Conference
• Year: 2009
• Where: FPGA
• Authors: Daniel L. Ly, Paul Chow
• Keywords: FPGA 2009, Hardware, Multi-purpose Hardware Framework, Neural Network, Restricted Boltzmann Machine