High Performance FPGA Implementation of the Mersenne Twister

Efficient generation of random and pseudorandom sequences is of great importance to a number of applications [4]. In this paper, an efficient implementation of the Mersenne Twister is presented. The proposed architecture has the smallest footprint of all published architectures to date and occupies only 330 FPGA slices. Partial pipelining and sub-expression simplification has been used to improve throughput per clock cycle. The proposed architecture is implemented on an RC1000 FPGA Development platform equipped with a Xilinx XCV2000E FPGA, and can generate 20 million 32 bit random numbers per second at a clock rate of 24.234 MHz. A through performance analysis has been performed, and it is observed that the proposed architecture clearly outperforms other existing implementations in key comparable performance metrics.

• Type: Conference
• Year: 2008
• Where: DELTA
• Authors: Shrutisagar Chandrasekaran, Abbes Amira
• Keywords: DELTA 2008, FPGA Development Platform, FPGA Slices, Information Management, Xilinx XCV2000E FPGA