A high-resolution and fast-conversion time-to-digital converter

This paper describes a design of time-to-digital converter (TDC), which has the features of high-resolution and fast Conversion. With the aid of the gate delay difference technique, the TDC can achieve a sub-gate delay resollition. The flasbtype operation enables the TDC to resolve the time difference for fine conversion in less than one reference clack cycle. The DNL can be less than iO.03LSB and INL less than +O.MLSB. We confirm the results based on 0.35um CMOS process technology.

• Type: Conference
• Year: 2003
• Where: ISCAS
• Authors: Chorng-Sii Hwang, Poki Chen, Hen-Wai Tsao
• Keywords: Gate Delay Difference, ISCAS 2003, Reference Clack Cycle, Sub-gate Delay Resollition