High Speed Switch Scheduling for Local Area Networks

Current technology trends make it possible to build communication networks that can support high performance distributed computing. This paper describes issues in the design of a prototype switch for an arbitrary topology point-to-point network with link speeds of up to one gigabit per second. The switch deals in xed-length ATM-style cells, which it can process at a rate of 37 million cells per second. It provides high bandwidth and low latency for datagram tra c. In addition, it supports real-time tra c by providing bandwidth reservations with guaranteed latency bounds. The key to the switch's operation is a technique called parallel iterative matching, which can quickly identify a set of con ict-free cells for transmission in a time slot. Bandwidth reservations are accommodated in the switch by building a xed schedule for transporting cells from reserved ows across the switch; parallel iterative matching can ll unused slots with datagram tra c. Finally, we note that parallel it...

• Type: Conference
• Year: 1992
• Where: ASPLOS
• Authors: Thomas E. Anderson, Susan S. Owicki, James B. Saxe, Charles P. Thacker
• Keywords: ASPLOS 1992, Bandwidth Reservations, Datagram Tra C, Parallel Iterative Matching, Programming Languages