High-throughput dual-mode single/double binary map processor design for wireless wan

In this paper we present the VLSI implementation of a high-throughput enhanced Max-log-MAP processor that supports both single-binary (SB) and double-binary (DB) convolutional turbo codes. The combined hybrid-window (HW) and parallel-window (PW) MAP decoding is introduced to support arbitrary frame sizes with high

• Type: Conference
• Year: 2008
• Where: SIPS
• Authors: Chun-Yu Chen, Cheng-Hung Lin, An-Yeu Wu
• Keywords: Arbitrary Frame, Convolutional Turbo Codes, Signal Processing, SIPS 2008, VLSI Implementation