High Throughput Multi-port MT19937 Uniform Random Number Generator

ct There have been many previous attempts to accelerate MT19937 using FPGAs but we believe that we can substantially improve the previous implementations to develop a higher throughput and more area time efficient design. In this paper we first present a single port design and then present an enhanced 624 port hardware implementations of the MT19937 algorithm that has a throughput of 119.6×109 32 bit random numbers per second, which is more than 17 times that of the previously best published uniform random number generator. Furthermore it has the lowest area time metric of all the currently published FPGA based pseudo uniform random number generators.

• Type: Conference
• Year: 2007
• Where: PDCAT
• Authors: Vinay Sriram, David Kearney
• Keywords: Distributed And Parallel Computing, PDCAT 2007, Random Number, Random Number Generators, Uniform Random Number