Highly scalable parallel parametrizable architecture of the motion estimator

In this paper a parametrizable architecture of a motion estimator (ME) is presented. The ME is designed as a generic full pixel calculation module which can be adopted for dierent video standards. The parameters by which the ME is described allow for a variety of architecture implementations. The parameters specify the level of parallelism re ected by multiple allocation of computational resources, and the use of congurable cache memories. The obtained VHDL description of the ME module is well suited for VLSI implementation.

• Type: Conference
• Year: 1997
• Where: DATE
• Authors: Radim Cmar, Serge Vernalde
• Keywords: DATE 1997, Di Erent Video, Gurable Cache Memories, Hardware, Pixel Calculation Module