How Does Resource Utilization Affect Fault Tolerance?

Many fault-tolerant architectures are based on the single-fault assumption, hence accumulation of dormant faults represents a potential reliability hazard. Based on the example of the fail-silent “Time-Triggered Architecture” we study sources and effects of dormant faults. We identify software as being more prone to dormant faults than hardware. By means of modeling we reveal a high sensitivity of the MTTF to the existence of even a small amount of irregularly used resources. We propose on-line testing as a means of coping with dormant faults and sketch an appropriate test strategy.

• Type: Conference
• Year: 2000
• Where: DFT
• Authors: Andreas Steininger, Christoph Scherrer
• Keywords: DFT 2000, Dormant Faults, Many Fault-tolerant Architectures, Potential Reliability Hazard, VLSI