Hybrid NOrec: a case study in the effectiveness of best effort hardware transactional memory

Transactional memory (TM) is a promising synchronization mechanism for the next generation of multicore processors. Best-effort Hardware Transactional Memory (HTM) designs, such as Sun’s prototype Rock processor and AMD’s proposed Advanced Synchronization Facility (ASF), can efficiently execute many transactions, but abort in some cases due to various limitations. Hybrid TM systems can use a compatible software TM (STM) in such cases. We introduce a family of hybrid TMs built using the recent NOrec STM algorithm that, unlike existing hybrid approaches, provide both low overhead on hardware transactions and concurrent execution of hardware and software transactions. We evaluate implementations for Rock and ASF, exploring how the differing HTM designs affect optimization choices. Our investigation yields valuable input for designers of future best-effort HTMs.

• Type: Journal
• Year: 2011
• Where: ASPLOS
• Authors: Luke Dalessandro, François Carouge, Sean White, Yossi Lev, Mark Moir, Michael L. Scott, Michael F. Spear
• Keywords: ASPLOS 2011, Concurrent Execution, Hybrid Approaches, Programming Languages, Software Transactions