A HyperTransport 3 Physical Layer Interface for FPGAs

Abstract. This paper presents the very first implementation of a HyperTransport 3 physical layer interface for Field Programmable Gate Arrays. HyperTransport is a low latency, high bandwidth point-to-point interconnect technology that can be used to directly connect hardware accelerators to AMD’s Opteron CPUs. Providing support for HyperTransport 3 on FPGAs is highly relevant for increasing the performance of accelerators based on reconfigurable logic. This paper shows the challenges of such an implementation and novel ideas to solve them successfully. A new architecture is presented that uses Fast Serializer Logic to keep up with the increasing speeds of current host interface protocols. A solid evaluation is provided using a specially developed FPGA board as a verification platform.

• Type: Conference
• Year: 2009
• Where: ARC
• Authors: Heiner Litz, Holger Fröning, Ulrich Brüning
• Keywords: AMD’s Opteron CPUs, ARC 2009, Bandwidth Point-to-point Interconnect, Programmable Gate Arrays