ILP-based Instruction Scheduling for IA-64

The IA-64 architecture has been designed as a synthesis of VLIW and superscalar design principles. It incorporates typical functionality known from embedded processors as multiply/accumulate units and SIMD operations for 3D graphics operations. In this paper we present an ILP formulation for the problem of instruction scheduling for IA-64. In order to obtain a feasible schedule it is necessary to model the data dependences, resource constraints as well as additional encoding restrictions—the bundling mechanism. These different aspects represent subproblems that are closely coupled which gives the motivation for a modeling based on integer linear programming. The presented approach is divided into two phases which allows us to compute mostly optimal solutions with acceptable computation time.

• Type: Conference
• Year: 2001
• Where: LCTRTS
• Authors: Daniel Kästner, Sebastian Winkel
• Keywords: IA-64 Architecture, LCTRTS 2001, Restrictions—the Bundling Mechanism, Superscalar Design Principles, System Software