On the implementation of 128-pt FFT/IFFT for high-performance WPAN

- This paper deals with the efficient realization of a 128-pt FFT/IFFT processor for application in IEEE 802.15.3a standard. The 128-pt FFT/IFFT architecture has been designed by devolving it into one 8-pt and one 16-pt FFT. The 16-pt FFT was decomposed again and two separate 128-pt FFT algorithms have been developed, viz., 8x4x4 and 8x2x8. Their relative merits and demerits have been analyzed from the algorithm as well as implementation point of view. The architectures have been prototyped on a Virtex II FPGA. The results indicate that the 8x2x8 architecture is better suited for the above mentioned purpose.

• Type: Conference
• Year: 2005
• Where: ISCAS
• Authors: C. Huggett, K. Maharatna, K. Paul
• Keywords: 128-pt Fft/ifft, 16-pt Fft, ISCAS 2005, Separate 128-pt Fft