Implementation of Fast Address-Space Switching and TLB Sharing on the StrongARM Processor

The StrongARM processor features virtually-addressed caches and a TLB without address-space tags. A naive implementation therefore requires flushing of all CPU caches and the TLB on each context switch, which is very costly. We present an implementation of fast context switches on the architecture in both Linux and the L4 microkernel. It is based on using domain tags as address-space identifiers and delaying cache flushes until a clash of mappings is detected. We observe a reduction of the context-switching overheads by about an order of magnitude compared to the naive scheme presently implemented in Linux. We also implemented sharing of TLB entries for shared pages, a natural extension of the fast-context-switch approach. Even though the TLBs of the StrongARM are quite small and a potential bottleneck, we found that benefits from sharing TLB entries are generally marginal, and can only be expected to be significant under very restrictive conditions.

• Type: Conference
• Year: 2003
• Where: APCSAC
• Authors: Adam Wiggins, Harvey Tuch, Volkmar Uhlig, Gernot Heiser
• Keywords: APCSAC 2003, Fast Context Switches, StrongARM Processor Features, TLB Entries