Verification and validation are key issues for today's SoC design projects. This paper presents the implementation of a SystemC based environment for transaction-based verification and validation. This new environment will supersede the currently used verification environment, which has been in use in our company since 2002 and is based on Cadence TestBuilder. The new SystemC based environment shows the following benefits. The description of testcases is made in SystemC, which is a standardized programming language, whereas the TestBuilder based environment uses a dedicated test description language. A seamless embedding of SystemC models is possible, so that verification models from other vendors can be used, e.g. for bridges and bus interfaces. A cosimulation of HDL and SystemC is applicable, which is not possible with the TestBuilder based environment. During the development of the new environment special emphasis was laid on the integration into an industrial design flow and ...