Implementing Distributed Packet Fair Queueing in a Scalable Switch Architecture

To support the Internet's explosive growth and expansion into a true integrated services network, there is a need for cost-effective switching technologies that can simultaneously provide high capacity switching and advanced QoS. Unfortunately, these two goals are largely believed to be contradictory in nature. To support QoS, sophisticated packet scheduling algorithms, such as Fair Queueing, are needed to manage queueing points. However, the bulk of current research in packet scheduling algorithms assumes an output buffered switch architecture, whereas most high performance switches (both commercial and research) are input buffered. While output buffered systems may have the desired quality of service, they lack the necessary scalability. Input buffered systems, while scalable, lack the necessary quality of service features. In this paper, we propose the construction of switching systems that are both input and output buffered, with the scalability of input buffered switches and ...

• Type: Conference
• Year: 1998
• Where: INFOCOM
• Authors: Donpaul C. Stephens, Hui Zhang
• Keywords: Communications, Fair Queueing, INFOCOM 1998, Output Buffered Switch, Packet Scheduling Algorithms