Improving Area Efficiency of Residue Number System based Implementation of DSP Algorithms

Residue Number System based applications involve modulo-arithmetic which is typically implemented using look-up-tables (LUTs) for a small value of modulus. In this paper, we present a data coding technique to minimize the area of these LUTs when implemented using two level logic structures such as PLAs. We also present a technique that exploits the symmetry in these computations to further optimize the LUTs. Results show that area improvement of upto 66% can be achieved using these techniques.

• Type: Conference
• Year: 1999
• Where: VLSID
• Authors: M. N. Mahesh, Satrajit Gupta, Mahesh Mehendale
• Keywords: Data Coding Technique, Level Logic Structures, Residue Number System, VLSI, VLSID 1999