Improving the power-delay product in SCL circuits using source follower output stage

— This article explores the effect of using source follower buffers (SFB) at the output of source coupled logic (SCL) circuits. This technique can help to improve the power-delay product (PDP) of an SCL gate approximately by a factor of two. The proposed approach has been applied to improve the PDP in sub-threshold SCL circuits that have been developed for ultralow power applications. Designed in conventional digital 0.18µm CMOS technology, the proposed SCL gate utilizing SFB at the output achieves a PDP of 0.5fJ/fF/gate while the gate draws 10nA from a 0.6V supply voltage.

• Type: Conference
• Year: 2008
• Where: ISCAS
• Authors: Armin Tajalli, Frank K. Gürkaynak, Yusuf Leblebici, Massimo Alioto, Elizabeth J. Brauer
• Keywords: Hardware, ISCAS 2008, SCL Gate, Source Follower Buffers, Sub-threshold Scl Circuits