Indirect Tag Search Mechanism for Instruction Window Energy Reduction

Instruction window is a key component which extracts Instruction Level Parallelism (ILP) in modern out-of-order microprocessors. In order to exploit ILP for improving processor performance, instruction window size should be increased. However, it is difficult to increase the size, since instruction window is implemented by CAM whose power and delay are much large. This paper introduces a low power and scalable instruction window that replaces CAM with RAM. In this window, instructions are explicitly woken up. Evaluation results show that the proposed instruction window decreases

• Type: Conference
• Year: 2007
• Where: IEEECIT
• Authors: Shingo Watanabe, Akihiro Chiyonobu, Toshinori Sato
• Keywords: IEEECIT 2007, Information Technology, Instruction Level Parallelism, Instruction Window, Instruction Window Size