Informing Memory Operations: Providing Memory Performance Feedback in Modern Processors

Memory latency is an important bottleneck in system performance that cannot be adequately solved by hardware alone. Several promising software techniques have been shown to address this problem successfully in specific situations. However, the generality of these software approaches has been limited because current architectures do not provide a fine-grained, low-overhead mechanism for observing and reacting to memory behavior directly. To fill this need, we propose a new class of memory operations called informing memory operations, which essentially consist of a memory operation combined (either implicitly or explicitly) with a conditional branch-and-link operation that is taken only if the reference suffers a cache miss. We describe two different implementations of informing memory operations--one based on a cache-outcome condition code and another based on low-overhead traps--and find that modern in-order-issue and out-of-order-issue superscalar processors already contain the bulk...

• Type: Conference
• Year: 1996
• Where: ISCA
• Authors: Mark Horowitz, Margaret Martonosi, Todd C. Mowry, Michael D. Smith
• Keywords: Hardware, ISCA 1996, Memory Latency, Memory Operations, Software-based Memory Optimizations