Initial Experiences with Dreamy Memory and the RAMpage Memory Hierarchy

The RAMpage hierarchy moves main memory up a level to replace the lowest-level cache by an equivalent-sized SRAM main memory. This paper is a first look at the value of RAMpage to low-energy design. The approach used, dreamy memory, is to put DRAM in a lowpower mode, unless it is referenced. RAMpage has been shown to be effective in hiding relatively high-latency DRAM access, which applies to masking wake-up latency. Simulation results show that RAMpage provides a better overall speed-energy compromise than the conventional architecture used for comparison. The most energy-efficient RAMpage configuration in dreamy mode ran 3% faster and used 71% of the energy for DRAM of the best dreamy run of the conventional model. As compared with the best non-dreamy run time, the best dreamy time was 9% slower, but used under 17% of the energy for DRAM. The lowest-energy dreamy simulation used less than 16% of the DRAM energy of the fastest non-dreamy version, a very useful gain, given that DRAM us...

• Type: Conference
• Year: 2004
• Where: APCSAC
• Authors: Philip Machanick
• Keywords: APCSAC 2004, Computer Architecture, DRAM, Dreamy Memory, Energy-efficient Rampage Configuration