Instruction-based System-level Power Evaluation of System-On-A-Chip Peripheral Cores

Various system-level core-based power evaluation approaches for core types like microprocessors, caches, main memories, and buses, have been proposed in the past. Approaches for other types of components have been based either on the gatelevel, register-transfer level, or behavioral-level. We propose a new technique, suitable for a variety of cores like peripheral cores, that is the first to combine gate-level power data with a system-level simulation model written in C++ or Java. For that purpose, we investigated peripheral cores and decomposed their functionality into so-called instructions. Our technique addresses a core-based system design paradigm. We show that our technique is sufficiently accurate for making power-related system-level design decisions, and that its computation time is orders of magnitude smaller than lower-level simulation approaches. Keywords System-on-a-chip, low-power design, intellectual property, caches, cores, estimation, silicon platforms, system paramet...

• Type: Conference
• Year: 2000
• Where: ISSS
• Authors: Tony Givargis, Frank Vahid, Jörg Henkel
• Keywords: Hardware, ISSS 2000, Peripheral Cores, System-level Core-based Power, System-level Simulation Model