Integrated analysis of communicating tasks in MPSoCs

Predicting timing behavior is key to efficient embedded real-time system design and verification. Especially memory accesses and co-processor calls over shared communication networks, basic operations of every embedded application pose a challenge for precise system analysis. Current approaches to determine end-to-end latencies in parallel heterogeneous architectures either focus on system level and allow only limited task models, or focus on activities inside ent, abstracting system level influences by overestimations. In this paper, we identify feedbacks of the system behavior that directly or indirectly impact local execution. To tackle these complex interactions we present a novel technique to integrate an extended component level scheduling analysis with refined system level ap. Bringing the different levels of abstraction together allows the analysis of a new class of interacting applications and architectures – which could not be addressed on a single level alone. On the ...

• Type: Conference
• Year: 2006
• Where: CODES
• Authors: Simon Schliecker, Matthias Ivers, Rolf Ernst
• Keywords: CODES 2006, Component Level, Hardware-Software Codesign, Level Scheduling Analysis, Parallel Heterogeneous Architectures