Integrating Performance Monitoring and Communication in Parallel Computers

A large and increasing gap exists between processor and memory speeds in scalable cache-coherent multiprocessors. To cope with this situation, programmers and compiler writers must increasingly be aware of the memory hierarchy as they implement software. Tools to support memory performance tuning have, however, been hobbled by the fact that it is difficult to observe the caching behavior of a running program. Little hardware support exists specifically for observing caching behavior; furthermore, what support does exist is often difficult to use for making fine-grained observations about program memory behavior. Our work observes that in a multiprocessor, the actions required for memory performance monitoring are similar to those required for enforcing cache coherence. In fact, we argue that on several machines, the coherence/communication system itself can be used as machine support for performance monitoring. We have demonstrated this idea by implementing the FlashPoint memory perfo...

• Type: Conference
• Year: 1996
• Where: SIGMETRICS
• Authors: Margaret Martonosi, David Ofelt, Mark Heinrich
• Keywords: Hardware, Memory Performance, Memory Performance Monitoring, Performance Monitoring, SIGMETRICS 1996