Interconnect Driver Design for Long Wires in Field-Programmable Gate Arrays

Each new semiconductor technology node brings smaller, faster transistors and smaller, slower wires. In particular, long interconnect wires in modern FPGAs now require rebuffering at interior points in the wire. This paper presents a framework for designing and evaluating long, buffered interconnect wires in FPGAs with near-optimal delay performance using HSPICE-derived delays. Given a target physical wire length, width, and spacing, the method determines the number, size, and position of buffers required to obtain the fastest signal velocity for programmable interconnect. While traditional hand-calculations used for ideal repeater placement can be used, they are not very accurate and ignore practical constraints such as the overhead effects of front-end multiplexing and driving logic, Bfinite^ wire length, and a discrete number of repeaters. A metric introduced during the design is the Bpath delay profile^, or the arrival time of a signal at different points of a long wire. This metho...

• Type: Journal
• Year: 2008
• Where: VLSISP
• Authors: Edmund Lee, Guy Lemieux, Shahriar Mirabbasi
• Keywords: Bpath Delay Profile^, Interconnect, VLSISP 2008, Wire