L-CBF: a low-power, fast counting bloom filter architecture

—An increasing number of architectural techniques rely on hardware counting bloom filters (CBFs) to improve upon the enegy, delay and complexity of various processor structures. CBFs improve the energy and delay of membership tests by maintaining an imprecise and compact representation of a large set to be searched. This work studies the energy, delay, and area characteristics of two implementations for CBFs using full custom layouts in a commercial 0.13 µm fabrication technology. One implementation, S-CBF, uses an SRAM array of counts and a shared up/down counter. Our proposed implementation, L-CBF, utilizes an array of up/down linear feedback shift registers and local zero detectors. Circuit simulations show that for a 1K-entry CBF with a 15-bit count per entry, L-CBF

• Type: Conference
• Year: 2006
• Where: ISLPED
• Authors: Elham Safi, Andreas Moshovos, Andreas G. Veneris
• Keywords: Hardware Counting Bloom, ISLPED 2006, Linear Feedback Shift Registers, —An Increasing Number