An L2-miss-driven early register deallocation for SMT processors

The register file is one of the most critical datapath components limiting the number of threads that can be supported on a Simultaneous Multithreading (SMT) processor. To allow the use of smaller register files without degrading performance, techniques that maximize the efficiency of using registers through aggressive register allocation/deallocation can be considered. In this paper, we propose a novel technique to early deallocate physical registers allocated to threads that experience L2 cache misses. This is accomplished by speculatively committing the load-independent instructions and deallocating the registers corresponding to the previous mappings of their destinations, without waiting for the cache miss request to be serviced. The early deallocated registers are then made immediately available for allocation to instructions within the same thread as well as within other threads, thus improving the overall processor throughput. On the average across the simulated mixes of multi...

• Type: Conference
• Year: 2007
• Where: ICS
• Authors: Joseph J. Sharkey, Dmitry V. Ponomarev
• Keywords: Aggressive Register Allocation/deallocation, Deallocate Physical Registers, ICS 2007, Register Files, Theoretical Computer Science