Layered Switching for Networks on Chip

We present and evaluate a novel switching mechanism called layered switching. Conceptually, the layered switching implements wormhole on top of virtual cut-through switching. To show the feasibility of layered switching, as well as to confirm its advantages, we conducted an RTL implementation study based on a canonical wormhole architecture. Synthesis results show that our strategy suggests negligible degradation in hardware speed (1%) and area overhead (7%). Simulation results demonstrate that it achieves higher throughput than wormhole alone while significantly reducing the buffer space required at network nodes when compared with virtual cut-through. Categories and Subject Descriptors: B.4 [Hardware]: Input/Output Data Communications; General Terms: Design, Theory, Performance

• Type: Conference
• Year: 2007
• Where: DAC
• Authors: Zhonghai Lu, Ming Liu, Axel Jantsch
• Keywords: Canonical Wormhole Architecture, DAC 2007, Design Automation, Layered Switching Implements, Virtual Cut-through Switching