Living with Failure: Lessons from Nature?

- The resources available on a chip continue to grow, following Moore's Law. However, the major process by which the benefits of Moore's Law accrue, which is the continuing reduction in feature size, is predicted to bring with it disadvantages in terms of device reliability and parameter variability. The problems that this will bring are underlined by the predictions from an Intel commentator: within a decade we will see 100 billion transistor chips. That is the good news. The bad news is that 20 billion of those transistors will fail in manufacture and a further 10 billion will fail in the first year of operation. What does a 20-30% device failure rate mean for designers and what does it mean for production test? As a designer, I have some idea how to design for very low device failure rates. Redundancy, fault-tolerance and ECC are all approaches that can cope with very low failure rates. The basic assumption is that faults are infrequent so we only have to cope with one at ...

• Type: Conference
• Year: 2006
• Where: ETS
• Authors: Steve Furber
• Keywords: Device Failure Rates, ETS 2006, Failure Rate, Hardware, Moore's Law