Logic Restructuring for Delay Balancing in Wave-Pipelined Circuits: An Integer Programming Approach

In this paper we apply integer programming (IP) based techniques to the problem of delay balancing in wave-pipelined circuits. The proposed approach considers delays, as well as fan-in and fan-out associated with every node in the circuit. After a weighted graph representation of the circuit is formed a node collapsing procedure is used to preprocess (reduce the size of) the system and obtain the final formulation of the IP problem, which is solved by using a branch and bound heuristic to obtain a minimum delay in the circuit. We also compare the proposed technique with application – to the same problem – of a linear programming solver.

• Type: Conference
• Year: 2005
• Where: SYNASC
• Authors: Srivastav Sethupathy, Nohpill Park, Marcin Paprzycki
• Keywords: Delay Balancing, Node Collapsing Procedure, SYNASC 2005, Weighted Graph Representation