Logic soft errors in sub-65nm technologies design and CAD challenges

Logic soft errors are radiation induced transient errors in sequential elements (flip-flops and latches) and combinational logic. Robust enterprise platforms in sub-65nm technologies require designs with built-in logic soft error protection. Effective logic soft error protection requires solutions to the following three problems: (1) Accurate soft error rate estimation for combinational logic networks; (2) Automated estimation of system effects of logic soft errors, and identification of regions in a design that must be protected; and, (3) New cost-effective techniques for logic soft error protection, because classical fault-tolerance techniques are very expensive. Categories and Subject Descriptors B.8.1 [Performance and Reliability]: Reliability, Testing and faulttolerance. General Terms Design, Reliability. Keywords Architectural Vulnerability Factor, Built-In Soft Error Resilience, derating, error blocking, error detection, recovery, soft error.

• Type: Conference
• Year: 2005
• Where: DAC
• Authors: Subhasish Mitra, Tanay Karnik, Norbert Seifert, Ming Zhang
• Keywords: Computer Architecture, DAC 2005, Logic Soft Error, Soft Error, Soft Error Protection