A Low-Power Carry Skip Adder with Fast Saturation

In this paper, we present the design of a carry skip adder that achieves low power dissipation and high-performance operation. The carry skip adder's delay and power dissipation are reduced by dividing the adder into variable-sized blocks that balance the delay of inputs to the carry chain. This grouping reduces active power by minimizing extraneous glitches and transitions. Each block also uses highly optimized complementing carry lookahead logic to reduce delay. Compared to previous designs, the adder architecture decreases power consumption by reducing the number of transistors, logic levels, and glitches. A 32-bit carry skip adder design that uses our approach has been implemented in 130nm CMOS

• Type: Conference
• Year: 2004
• Where: ASAP
• Authors: Michael J. Schulte, Kai Chirca, John Glossner, Haoran Wang, Suman Mamidi, Pablo I. Balzola, Stamatis Vassiliadis
• Keywords: ASAP 2004, Carry Skip Adder, Hardware, Power Dissipation, Skip Adder Design