A low-power deblocking filter architecture for H.264 advanced video coding

Abstract— In this paper, a low-power deblocking filter architecture for H.264/AVC is proposed. A hybrid filtering order has been adopted to boost the speed of the deblocking filter process up to 208 clock cycles per 16x16 macroblock. The processing order of the filter is optimized to reduce power consumption and filter size and this is done by reducing memory access and raising the reusability of register blocks. A hardware implementation, under Samsung 0.18 µm standard cell library, consumes 18.34K gates at a clock frequency of 125MHz. Comparing to some stateof-the-art designs, the proposed architecture delivers the lowest level of power consumption while achieving similar speed of performance.

• Type: Conference
• Year: 2007
• Where: VLSI
• Authors: Jaemoon Kim, Sangkwon Na, Chong-Min Kyung
• Keywords: Deblocking filter, Deblocking filter Architecture, Power Consumption, Software Engineering, VLSI 2007