Low-power gated bus synthesis for 3d ic via rectilinear shortest-path steiner graph

In this paper, we propose a new approach for gated bus synthesis [16] with minimum wire capacitance per transaction in three-dimensional (3D) ICs. The 3D IC technology connects different device layers with through-silicon vias (TSV), which need to be considered differently from metal wire due to reliability issues and a larger footprint. Practically, the number of TSVs is bounded between layers; thus, we first devise dynamic programming and local search techniques to determine the optimal TSV locations. We then employ two approximation algorithms to generate a rectilinear shortestpath Steiner graph in each device layer. One algorithm extends the well-known greedy heuristic for the Rectilinear Steiner Arborescence problem and handles large cases with high efficiency. The other algorithm utilizes a linear programming relaxation and rounding technique which costs more time and generates a nearly-optimal Steiner graph. Experimental results show that our algorithms can construct shortes...

• Type: Journal
• Year: 2012
• Where: ISPD
• Authors: Chung-Kuan Cheng, Peng Du, Andrew B. Kahng, Shih-Hung Weng
• Keywords: Approximation Algorithms, Hardware, ISPD 2012, Linear Programming Relaxation, Rectilinear Steiner