Low power gated bus synthesis using shortest-path Steiner graph for system-on-chip communications

Power consumption of system-level on-chip communications is becoming more significant in the overall system-on-chip (SoC) power as technology scales down. In this paper, we propose a low power design technique of gated bus which can greatly reduce power consumption on state-of-the-art bus architectures. By adding demultiplxers and adopting a novel shortest-path Steiner graph, we achieve a flexible tradeoff between large power reduction versus small wirelength increment. According to our experiments, using the gated bus we can reduce on average 93.2% of wire capacitance per transaction, nearly half of bus dynamic power and on a scale of 5%10% of total system power. Categories and Subject Descriptors J.6 [Computer Applications]: Computer-aided design General Terms Algorithms, design, performance Keywords Gated bus, Steiner graph, power efficiency

• Type: Conference
• Year: 2009
• Where: DAC
• Authors: Renshen Wang, Nan-Chi Chou, Bill Salefski, Chung-Kuan Cheng
• Keywords: Bus Dynamic Power, DAC 2009, Design Automation, Keywords Gated Bus, Power Reduction Versus